Addressing Modes Computer Organization GATE Question 08

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Playlist for all videos on this topic: • Computer Organization and Architectur... • GATE Problem Solutions Addressing Modes Computer Organization CO Video lecture for gate exam • The first operand (destination) “A [R0]” uses indexed addressing mode with R0 as the index register. The second operand (source) “@ B” uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand). • The number of memory cycles needed during the execution cycle of the instruction is • Which is the most appropriate match for the items in the first column with the items in the second column • X. Indirect Addressing I. Array implementation • Y. Indexed addressing II. Writing relocatable code • Z. Base Register Addressing III. Passing array as parameter • In the absolute addressing mode the operand is inside the instruction the address of the operand in inside the instruction • the register containing the address of the operand is specified inside the instruction the location of the operand is implicit • Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side. • (1) A[I] = B[J] (a) Indirect addressing • (2) while (*A++); (b) Indexed addressing • (3) int temp = *x (C) Auto increment • Relative mode addressing is most relevant to writing a (1) Co-routines (2) Position independent code (3) Shareable code (4) Interrupt handler • Which of the following addressing modes are suitable for program relocation at run time?[1 mark] • (i) Absolute addressing • (ii) Based addressing • (iii) Relative addressing • (iv) Indirect addressing • (a) (i) and (iv) • (b) (i) and (ii) • (c) (ii) and (iii) • (d) (i), (ii) and (iv) • A CPU has 24 bit instruction, a program starts at address 300(in decimal). Which one of the following is legal program counter(all values in decimal) • a) 400 • b) 500 • c) 600 • d) 700 • A CPU has 2 modes, privileged and non-privileged. In order to change the mode from previledged to non-previledged • a) A hardware interrupt is needed • b) A software interrupt is needed. • c) A privileged instruction is needed. • d) A non-privileged instruction is need. • A CPU has 32 bit memory address and a 256Kb cache memory, the cache is organized as a 4 way set associative cache with cache block size of 16 bytes. • a) What is the number of sets in the cache. • b) What is the size of tag filled per cache block. • Which one the following is true for CPU having a single interrupt request line and a single interupt grant line. • a) Neither vector interrupt nor multiple interrupting devices are possible. • b) Vector interrupts are not possible but multiple interrupting devices are possible. • c) Both are possible. • d) Vector interrupt is possible but multiple interrupting devices are not possible. • A CPU generates 32 bit virtual addresses, the page size is 4KB, the processor has a TLB which can hold a total of 128 page table enteries and is 4 way set associative. The minimum size of TLB tag is • A 2 leave memory is having 140 ns average access time without the leave, 30 ns with leave. If the fastest memory access time is 20 ns . What is the hit ratio: • Which of the following is/are true of the auto-increment addressing mode? • I. It is useful in creating self-relocating code. • II. If it is included in an Instruction Set Architecture, • then an additional ALU is required for effective address • calculation. • III.The amount of increment depends on the size of the data • item accessed. • Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory? • (A) Immediate Addressing • (B) Register Addressing • (C) Register Indirect Scaled Addressing • (D) Base Indexed Addressing

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