Youtor
Simulating a VHDLVerilog code using Modelsim SE
>> YOUR LINK HERE: ___ http://youtube.com/watch?v=9uSWnVwk_vg
ModelSim is a very popular simulation tool among VHDL/Verilog programmers. In this video I try to show you how to compile and simulate a simple VHDL code. The method is the same even if the codes are in Verilog. • I am using the free student version of Modelsim for this. • VHDL Tutorial Blog: http://vhdlguru.blogspot.com/ • Verilog Tutorial Blog: https://verilogcodes.blogspot.com/
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