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In this video we have learned about the types of FPGA and FPGA Design Flow. There are mainly 3 types of FPGA: • SRAM based FPGA • Anti-fuse programmable based FPGA • Flash based FPGA • This video will be helpful for understanding the working of different types of fpga and the design flow in detail. This video is for both undergraduates and post graduate students of Electronics. • FPGA Design Flow is classified into frontend and Backend. Frontend includes the design specification, architecture design, RTL modeling, verification and synthesis however Backend includes the floor planning, placement, routing and the timing analysis. • References : www.xilinx.com , www.ni.com • ------- • Join our Telegram group for more discussion and get some outstanding materials for exams and interviews along with job/internship opening update : https://t.me/+1Inrc6MglUcwMGNl • ------- • Don't miss the verilog tutorial videos for beginners: • Introduction to HDL | What is HDL? | #1 | Verilog in English • • Introduction to HDL | What is HDL? | ... • Level of abstraction in Verilog | #2 | Verilog in English • • Level of abstraction in Verilog | #2 ... • Modules and Instantiation in Verilog | #3 | Verilog in English • • Modules and Instantiation in Verilog ... • Simulation, Synthesis and Design methodology in Verilog | #4 | Verilog in English • • Simulation, Synthesis and Design meth... • Data types in Verilog | #5 | Introduction | Verilog in English | VLSI Point • • Data types in Verilog | #5 | Introduc... • Net Data type in Verilog | #6 | Verilog in English | VLSI Point • • Net Data type in Verilog | #6 | Veril... • Reg Datatype in Verilog | # 7 | Verilog in English | VLSI Point • • Reg Datatype in Verilog | # 7 | Veril... • Vectors, Arrays, Memories, Parameters, Strings in Verilog | #8 | verilog in English | VLSI Point • • Vectors, Arrays, Memories, Parameters... • Operators in Verilog | #9 | Verilog in English | VLSI Point • • Operators In Verilog | #9 | Verilog i... • Practice-Set | #10 | Verilog in English | VLSI Point • • Practice-Set | #10 | Verilog in Engli... • Gate Level Modeling | #11 | Verilog in English | VLSI Point • • Gate Level Modeling | #11 | Verilog ... • Dataflow Modeling | #12 | Verilog in English | VLSI Point • • Dataflow Modeling | #12 | Verilog in ... • Behavioral Modeling | #13 | Verilog in English | VLSI Point • • Behavioral Modeling | #13 | Verilog ... • Compiler directive System tasks in Verilog | #14 | Verilog in English • • Compiler directive System tasks in ... • Task and Functions in Verilog | #15 | Verilog in English • • Task and Functions in Verilog | #15 |... • Test Bench writing in Verilog | #16 | Verilog in English | VLSI POINT • • Test Bench writing in Verilog | #16 ... • Reference- verilog HDL : A Guide to Digital Design and Synthesis • By Samir palnitkar

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