SR latch

YOUR LINK HERE:

http://youtube.com/watch?v=U_aVMNsy4Q0

In order to hold (preserve) a state, both of the external trigger inputs must be equal to logic “1”. The state of the circuit can be changed by pulling the set input or reset input to zero. • A NAND-based SR latch responds to an active low input signals, while the • NOR-based SR latch responds to an active high inputs. The small circles at the S and R input terminals indicate that the circuit responds to active low input signals. • For Digital Electronics Review Part-1 Click • • Digital Electronics Review Part-1 • For Digital Electronics Review Part-2 Click • • Digital Electronics Review Part - 2 • For Digital Electronics Review Part-3 Click • • Digital Electronics Review Part - 3 • For Introduction to CMOS Logic Family Click • • Introduction to CMOS Logic Family • For CMOS Logic Design of XOR and XNOR Click • • CMOS Logic Circuit Design for XOR and... • For CMOS Logic Circuit Design for NOT, NAND and NOR Gate Click • • CMOS Logic Circuit Design for NOT, NA... • For CMOS Logic Circuit Design for AND and OR Gate Click • • CMOS Logic Circuit Design for AND and... • For CMOS Logic Circuit Design for different Boolean Expression Click • • CMOS Logic Circuit Design for differe...

#############################

New on site