Youtor
VLSI Lecture 7e Basic Timing Constraints
>> YOUR LINK HERE: ___ http://youtube.com/watch?v=gEwNvszSh3c
Bar-Ilan University 83-313: Digital Integrated Circuits • This is Lecture 7 of the Digital Integrated Circuits (VLSI) course at Bar-Ilan University. In this course, I cover VLSI circuit design, starting with the technology and through the design of complex digital circuits, such as multipliers and memory blocks. • Lecture 7 discusses Sequential Synchronous Circuit Design, including the overall approach, timing constraints and the design of sequential elements. Section 7e presents the basic timing constraints of synchronous logic design, i.e., max-delay (setup) and min-delay (hold). • • Lecture slides can be found on the EnICS Labs web site at: • https://enicslabs.com/academic-course... • All rights reserved: • Prof. Adam Teman • Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs • Faculty of Engineering, Bar-Ilan University
#############################
