Vitis HLS

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0:00 Introduction to High Level Synthesis • 8:20 Example function • 10:39 Introduction to Vitis HLS • 17:43 C Simulation • 20:15 C Synthesis • 28:30 Seeing the generated Verilog • 32:42 Thoughts on increasing the performance • 38:19 Using Vitis HLS to optimise performance • 57:28 Using main memory

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