CMOS Transistor Logic Gates and SPICE Analysis LTSpice oregano etc

>> YOUR LINK HERE: ___ http://youtube.com/watch?v=kiDl0AdmkbQ

This video shows CMOS transistor logic gates (NAND, AND, NOR, and OR) and shows how to use SPICE programs to analyze the circuits. It shows LTSpice (for Windows and Mac) as well as Oregano, ngspice, spice2g.6, and nutmeg (for UNIX and Linux). SPICE is also available for other platforms (MS-DOS, Amiga, VAX, etc.) - but not covered in this video. • Refer to my other videos on how CMOS NAND and NOR circuits work as well as how they can be created using a gate array integrated circuit. • NOR Gate Transistor Design and CMOS Gate Array Implementation: • • NOR Gate Transistor Design and CMOS G... • NAND Gate Transistor Design and CMOS Gate Array Implementation: • • NAND Gate Transistor Design and CMOS ... • Here are the spice files: • CMOSnand6d • M1 N001 A F N001 PMOS • M2 N001 B F N001 PMOS • M3 F A P001 0 NMOS • M4 P001 B 0 0 NMOS • V1 N001 0 5 • V2 A 0 PULSE(1 4 1 0 0 1 2) • V3 B 0 PULSE(.95 4.05 .5 0 0 .5 1) • .model NMOS NMOS • .model PMOS PMOS • .tran .1 4 • .backanno • .plot tran A B F • .end • CMOSnor6d • V1 N001 0 5 • V2 A 0 PULSE(1 4 1 0 0 1 2) • V3 B 0 PULSE(.95 4.05 .5 0 0 .5 1) • M1 N001 A P001 N001 PMOS • M2 P001 B F N001 PMOS • M3 F A 0 0 NMOS • M4 F B 0 0 NMOS • .model NMOS NMOS • .model PMOS PMOS • .tran .1 4 • .backanno • .plot tran A B F • .end • CMOSand6d • V1 N001 0 5 • V2 A 0 PULSE(1 4 1 0 0 1 2) • V3 B 0 PULSE(.95 4.05 .5 0 0 .5 1) • M1 N001 A P001 0 NMOS • M2 P001 B F 0 NMOS • M3 F A 0 N001 PMOS • M4 F B 0 N001 PMOS • .model NMOS NMOS • .model PMOS PMOS • .tran .1 4 • .backanno • .plot tran A B F • .end • CMOSor6d • M1 N001 A F 0 NMOS • M2 N001 B F 0 NMOS • M3 F A P001 N001 PMOS • M4 P001 B 0 N001 PMOS • V1 N001 0 5 • V2 A 0 PULSE(1 4 1 0 0 1 2) • V3 B 0 PULSE(.95 4.05 .5 0 0 .5 1) • .model NMOS NMOS • .model PMOS PMOS • .tran .1 4 • .backanno • .plot tran A B F • .end • Better AND and OR: • CMOSandc • M1 N001 A N002 N001 PMOS • M2 N001 B N002 N001 PMOS • M3 N002 A P001 0 NMOS • M4 P001 B 0 0 NMOS • V1 N001 0 5 • V2 A 0 PULSE(1 4 1 0 0 1 2) • V3 B 0 PULSE(.95 4.05 .5 0 0 .5 1) • M5 N001 N002 F N001 PMOS • M6 F N002 0 0 NMOS • .model NMOS NMOS • .model PMOS PMOS • .tran .1 4 • .backanno • .plot tran A B F • .end • CMOSorc • V1 N001 0 5 • V2 A 0 PULSE(1 4 1 0 0 1 2) • V3 B 0 PULSE(.95 4.05 .5 0 0 .5 1) • M1 N001 A P001 N001 PMOS • M2 P001 B N002 N001 PMOS • M3 N002 A 0 0 NMOS • M4 N002 B 0 0 NMOS • M5 N001 N002 F N001 PMOS • M6 F N002 0 0 NMOS • .model NMOS NMOS • .model PMOS PMOS • .tran .1 4 • .backanno • .plot tran A B F • .end • And might as well throw in a NOT: • CMOSnot • V1 N001 0 5 • V3 A 0 PULSE(.95 4.05 .5 0 0 .5 1) • M5 N001 A F N001 PMOS • M6 F A 0 0 NMOS • .model NMOS NMOS • .model PMOS PMOS • .tran .1 4 • .backanno • .plot tran A B F • .end

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