* Digitronix (updated 2024-10-01) ~ youtor.org

Digitronix (updated 2024-10-01)

SERIAL COMMUNICATION BETWEEN PC amp MICROCONTROLER [upl. by Ailuj]
Duration: 3:49
990 weergaven | 16 jun. 2016
Basic Image Processing in Python with Pynq FPGA amp USB Webcam [upl. by Mariquilla435]
Duration: 6:15
11,1K weergaven | 31 jan. 2017
Creating Custom PYNQ Overlay with VIVADO HLS IPI and Jupyter [upl. by Germin]
Duration: 22:44
13,8K weergaven | 27 mrt. 2019
ALU Design implemented on Spartan 3E Nexys 2 FPGA [upl. by Sayles]
Duration: 5:25
1,4K weergaven | 8 jul. 2016
DJetronic Fuel Economy [upl. by Anairam]
Duration: 3:52
3,1K weergaven | 10 apr. 2018
Multichannel4 Channel Video Overlay with Zynq FPGA [upl. by Donaghue]
Duration: 3:52
896 weergaven | 5 mrt. 2019
Nexys 4 DDR FPGA based ALU design with Seven Segment [upl. by Heng]
Duration: 2:55
1,6K weergaven | 23 jan. 2019
Design and Simulation of ALU on ModelSim [upl. by Essilevi]
Duration: 9:12
4,1K weergaven | 20 apr. 2018
How to write 12Ghs Keccak algorithm on VHDL targeting VCU1525 [upl. by Nitin]
Duration: 30:20
1,6K weergaven | 25 feb. 2019
Tutorial on Writing Simulation Testbench on Verilog with VIVADO [upl. by Cestar444]
Duration: 11:19
2,7K weergaven | 19 apr. 2018
Intel Quartus Tool ANDOR gate Design amp Simulation with VWF method [upl. by Nealon]
Duration: 9:03
4,1K weergaven | 21 apr. 2019
FPGA Design with MATLABSimulink System GeneratorUdemy Course [upl. by Corotto992]
Duration: 3:59
10,4K weergaven | 29 jan. 2019
Advance Verilog Design Overview Data Types Syntax and Semantics [upl. by Erl]
Duration: 22:06
410 weergaven | 3 mrt. 2019
Ultra96 FPGA First Boot Up amp GPIO Control [upl. by Anesusa]
Duration: 5:26
2,6K weergaven | 19 dec. 2018
PYNQZ2 Unboxing and Demo [upl. by Haile]
Duration: 4:19
7,4K weergaven | 14 mrt. 2019
Vending Machine Design amp Implemented on Spartan 3E Nexys 2FPGA [upl. by Wachtel]
Duration: 3:57
743 weergaven | 8 jul. 2016
Numato Mimas V2 Building Github Project of VGA amp Seven Segment [upl. by Meggy842]
Duration: 10:41
1,9K weergaven | 20 apr. 2019
8 bit ALU Design in VHDL with Xilinxs Tool [upl. by Chane]
Duration: 15:53
8,7K weergaven | 29 jan. 2019
MATLAB based OFDM Receiver Design and Simulation Session [upl. by Chassin834]
Duration: 14:01
5,5K weergaven | 22 feb. 2019
Verilog vs System Verilog [upl. by Sybila]
Duration: 9:19
2,7K weergaven | 15 jan. 2019





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