What are Setup and Hold Times of a CMOS Latch Explanation

>> YOUR LINK HERE: ___ http://youtube.com/watch?v=1LRRUtgsM2s

Explanation of what are setup and hold times of a CMOS latch with an active high enable. The latch closes on the falling edge of enable.

YouTube Editor, Digital, Logic, Boolean, setup, hold, latch, flip flop, AND, NAND, NOR, OR, EXOR, EXNOR, NMOS, PMOS, CMOS, Clock, Data, India, UK, Australia, USA, EE, IEEE
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