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eInfochips Shortens Runtime on 300M Gate Count SoCs with Innovus Implementation System
>> YOUR LINK HERE: ___ http://youtube.com/watch?v=S1X4tYYahZ8
Designing a large-scale SoC? Watch this 3-minute video to hear how Nilesh Ranpura, a project manager at eInfochips, and Dhaval Parikh, sr. tech lead, physical design, for the company, shortened runtime and improved productivity on a three SoC platform with 300M gate counts. Their main worry was meeting the 12-month delivery schedule, but they alleviated their concerns using the Cadence® Innovus™ Implementation System. Learn from the best practices they share in this video. And, for more information on the Innovus Implementation System, visit: http://bit.ly/1ZWZ7X3
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