Whats New in SystemVerilog UVM 12 Objections

>> YOUR LINK HERE: ___ http://youtube.com/watch?v=V53JakdIUQQ

Objections example: http://www.edaplayground.com/s/4/979 • set_automatic_phase_objection example: http://www.edaplayground.com/s/4/1037 • In this video we cover several UVM 1.2 changes related to objections: • set_propagate_mode to 0 for performance improvement • uvm_phase has get_objection_count function • easier to drop all objections • set_automatic_phase_objection for uvm_sequence • This video series covers the changes and new features introduced in UVM 1.2 (Universal Verification Methodology). It is intended for engineers who are already somewhat familiar with UVM. • UVM 1.2 Class Reference: http://eda-playground.readthedocs.org... • Recommend viewing in 720p quality or higher. • About EDA Playground: • EDA Playground is a web browser-based integrated development environment (IDE) for simulation of SystemVerilog, Verilog, VHDL, and other HDLs. EDA Playground is a free web application that allows users to edit, simulate, share, synthesize, and view waves for hardware description language (HDL) code. It is the first online HDL development environment and waveform viewer for the semiconductor industry. • EDA Playground homepage: http://www.edaplayground.com • Engineers have used EDA Playground for: • -- creating hands-on training for students • -- demonstrating best practices to other engineers • -- asking SystemVerilog questions on StackOverflow and other online forums • -- testing candidates' coding skills during technical interviews (phone and in-person) • -- quick prototyping -- trying something before inserting the code into a large code base • -- checking whether their RTL syntax/code is synthesizable • EDA Playground is actively seeking partners to integrate additional EDA tools. Future tools will include formal verification, linting, and analog and mixed-signal support.

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